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Autosync Deflection Controller (ASDC) TDA4855
MBG592 MBG593
handbook, halfpage
handbook, halfpage
IVOUT1 VEWDRV
IVOUT2
"l1(1) "l2
VDC(EWDRV)
t
t
(1) "I1 is VPOS adjustment centred; maximum amplitude setting at
VAMP (pin 18) and VGA presets disabled.
"I2 "I1
"VPOS = --------------------- × 100%
-
2 × "I1 "EWWID = 0 to VDC(EWDRV).
Fig.6 VEWDRV as a function of time.
Fig.5 IVOUT1 and IVOUT2 as functions of time.
MBG594
MBG595
handbook, halfpage
handbook, halfpage
IVOUT1
VEWDRV
"l2/"t
IVOUT2
VTRP(EWDRV)
"l1(1)/"t
t
t
(1) "I1 is VSCOR = 0%; maximum amplitude setting at VAMP
(pin 18) and VGA presets disabled.
"I1 "I2
"VSCOR = --------------------- × 100%
-
"I1 "EWTRP = ±VTRP(EWDRV).
Fig.8 VEWDRV as a function of time.
Fig.7 IVOUT1 and IVOUT2 as functions of time.
1996 Jul 18 23
Philips Semiconductors Preliminary specification
Autosync Deflection Controller (ASDC) TDA4855
Pulse diagrams
handbook, full pagewidth
horizontal oscillator sawtooth
at HCAP (pin 29)
horizontal sync pulse
PLL1 control current
-
+
at HPLL1 (pin 26)
video clamping pulse
vertical blanking level
at CLBL (pin 16)
triggered on
trailing edge of horizontal sync
line flyback pulse
at HFLB (pin 1)
PLL2 control current
+
at HPLL2 (pin 31)
PLL2
control range
line drive pulse at HDRV (pin 7)
45 to 48% of line period
horizontal focus parabola
at FOCUS (pin 10)
MBG598
Fig.9 Pulse diagram for horizontal part.
1996 Jul 18 24
Philips Semiconductors Preliminary specification
Autosync Deflection Controller (ASDC) TDA4855
handbook, full pagewidth 4.0 V automatic trigger level
3.8 V synchronized trigger level
vertical oscillator sawtooth
at VCAP (pin 24)
1.4 V
vertical sync pulse
inhibited
internal trigger
inhibit window
(typical 6.7 ms)
vertical blanking pulse
at CLBL (pin 16)
IVOUT1
differential output currents
VOUT1 (pin 13) and
VOUT2 (pin 12)
IVOUT2
7.0 V maximum
tip-parabola
EW parabola 3 V (p-p) maximum
EW drive waveform
at EWDRV (pin 11)
DC shift 4 V maximum
LOW level 1.2 V fixed
MBG597
Fig.10 Pulse diagram for vertical part.
1996 Jul 18 25
Philips Semiconductors Preliminary specification
Autosync Deflection Controller (ASDC) TDA4855
composite sync (TTL)
handbook, full pagewidth
at HSYNC (pin 15)
internal integration of
composite sync
internal vertical
trigger pulse
PLL1 control voltage
at HPLL1 (pin 26)
clamping and blanking
pulses at CLBL (pin 16)
MGC947
a. Reduced influence of vertical sync on horizontal phase.
handbook, full pagewidth
composite sync (TTL)
at HSYNC (pin 15)
clamping and blanking
pulses at CLBL (pin 16)
MBG596
b. Generation of video clamping pulses during vertical sync with serration pulses.
Fig.11 Pulse diagrams for composite sync applications.
1996 Jul 18 26
Philips Semiconductors Preliminary specification
Autosync Deflection Controller (ASDC) TDA4855
APPLICATION INFORMATION
handbook, full pagewidth
2 VHDRV
VCC
Vi
R6
7
6
3 VBDRV L
D2
S Q
OTA
2.5 V
TR1
HORIZONTAL
R Q
OUTPUT
INVERTING
STAGE
BUFFER
DISCHARGE
5 3 4
D1
1 horizontal
VBIN VBOP
R5
flyback pulse
R1 4 VBSENS
C4 R4
C1
R2
C2
MBG599
CBOP
R3
>4.7 nF
EWDRV
For f
BOP (pin 3). See Chapter Characteristics , Row Head B+ control section (see Figs 12 and 13) .
a. Feedback mode application.
handbook, full pagewidth
1 horizontal
flyback pulse
2 VHDRV
ton
3 VBDRV
td(BDRV) toff(min)
VBSENS = VBOP
VRESTART(BSENS)
4 VBSENS
VSTOP(BSENS)
MBG600
b. Waveforms for normal operation. c. Waveforms for fault condition.
Fig.12 Application and timing for feedback mode.
1996 Jul 18 27
Philips Semiconductors Preliminary specification
Autosync Deflection Controller (ASDC) TDA4855
handbook, full pagewidth horizontal
VCC
2 VHDRV
flyback pulse
1
R4
7
6
HORIZONTAL
INVERTING
OUTPUT
S Q BUFFER
STAGE
OTA
2.5 V
R Q
EHT
D2
3 VBDRV transformer
5 IMOSFET
DISCHARGE
TR1
5 3 4
VBOP VBSENS
EHT adjustment R1 R2
VBIN
R3
MBG601
D1 4
TR2
CBSENS
power-down
C1
>2 nF
CBOP > 4.7 nF
a. Forward mode application.
handbook, full pagewidth
1 horizontal
flyback pulse
2 VHDRV
ton
3 VBDRV
td(BDRV) toff
(discharge time of CBSENS)
VBOP VBOP
4 VBSENS
VRESTART(BSENS)
VSTOP(BSENS)
5 IMOSFET
MBG602
b. Waveforms for normal operation. c. Waveforms for fault condition.
Fig.13 Application and timing for feed forward mode.
1996 Jul 18 28
Philips Semiconductors Preliminary specification
Autosync Deflection Controller (ASDC) TDA4855
Start-up and shut-down sequence
handbook, full pagewidth
MBG555
VCC
VCC > 8.5 V
8.5 V continuous blanking off
PLL2 enabled
and
VHPLL2 > 4.4 V
frequency detector enabled
VCC > 8.2 V
8.2 V video clamping pulse enabled
BDRV enabled and
VHPLL2 > 3.7 V
VOUT1 and VOUT2 enabled
5.8 V PLL2 soft start sequence begins(1)
4.0 V continuous blanking CLBL (pin 16) activated
time
(1) See Fig.15 for PLL2 soft-start.
a. Start-up sequence.
MBG554
handbook, full pagewidth
VCC
8.5 V continuous blanking CLBL (pin 16) activated
PLL2 disabled
frequency detector disabled
8.0 V video clamping pulse disabled
BDRV floating
VOUT1 and VOUT2 floating
5.6 V HDRV floating
4.0 V continuous blanking disappears
time
b. Shut-down sequence.
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